1. Field of the Invention
The present invention relates to a semiconductor memory device and a control method thereof, for example, a semiconductor memory device including static memory cells and a control method thereof.
2. Description of the Related Art
Static random access memorys (SRAMs) are well known as an example of semiconductor memory devices. SRAM cells (six-transistor SRAM cells) each being formed of six metal oxide semiconductor (MOS) transistors are used as memory cells forming SRAMs.
Each six-transistor SRAM cell has two inverters, and has a structure in which an output terminal of one inverter is connected to an input terminal of the other inverter. Further, each six-transistor SRAM cell has two transfer gates which connect data storage nodes of the inverters to bit lines when data is read and when data is written.
A static noise margin (SNM) is known as an index of an operation margin of an SRAM. The SNM is a value obtained by superposing input/output characteristics of two inverters when a word line is selected and a bit line is precharged to a power supply voltage, and corresponds to a length of a side of a square which is drawn between the curves.
In recent years, the size of transistors used for memory cells has been reduced, to increase the integration of semiconductor memory devices. Further, the threshold voltage of transistors has also been reduced, in correspondence with reduction in power supply voltage. Reduction of these values has caused the problem that variations in threshold voltage of transistors forming memory cells increase. Further, there has been caused the problem that the SNM is reduced by influence of variations in threshold voltage of transistors forming memory cells.
Therefore, in memory cells having low data retention stability due to a low SNM, there is the problem that storing states of the inverter pair storing data are inverted and data is destructed, when data is read from memory cells or a word line connected to memory cells is activated to write data in memory cells.
Further, as a related technique, the following document discloses an SRAM which can increase data retention property by increasing the SNM in data reading.
Document: Leland Chang et al. “Stable SRAM Cell Design for the 32 nm Node and Beyond”, 2005 Symposium on VLSI Technology Digest of Technical Papers, pp. 128-129